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Syllabus | B. Tech. Electronics & Communication Engineering | VLSI Design

13040606 VLSI Design L T P C
Version1.1   3 1 0 3
Pre-requisites//Exposure Digital Design
co-requisites  

 

Course Objectives

The student will learn and understand

  1. Transistor-Level CMOS Logic Design.
  2. Estimation and Optimization of combinational circuits using RC delay models and logical efforts.

Course Outcomes

The students will be able to

  1. Create models of moderately sized CMOS circuits that realize specified digital functions.
  2. Have an understanding of the characteristics of CMOs circuit construction.

Catalog Description 

A course in VLSI semiconductor devices, modern CMOS technology, crystal growth, fabrication, and basic properties of silicon wafers. It will focus on lithography, thermal oxidation, (Si/Si)2, interface, dopant diffusion, ion implantation, thin film deposition, etching, and back-end technology.

Text Books

1.Sung-Mo Kang & Yusuf Leblebici, “CMOS Digital Integrated Circuits – Analysis and Design”, 3rd Edition, Tata McGraw-Hill, New Delhi, 2003.

  1. Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital Integrated Circuits: a design perspective”, 2nd Edition, Pearson Education, 2003.

Reference Books

  1. David A. Hodges, Horace G. Jackson, Resve A. Saleh, “Analysis and Design of Digital Integrated Circuits: In Deep Submicron Technology”, McGraw, 2003.
  2. David A. Johns and Ken Martin, “Analog Integrated Circuit Design” John Wiley and Sons Inc., 1997.
  3. Neil Weste and David Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, 4th Edition, Addison-Wesley, 2010
  4. John P.Uyemura, “CMOS Logic Circuit Design”, Springer International Edition.2005.Logic Circuit Design”, Springer International Edition.2005. 

Course Content 

Unit – I: MOS TRANSISTOR                                                                            

9 lecture hours

Introduction to MOS Transistor Theory: nMOS, pMOS Enhancement Transistor, MOSFET as a Switch, Threshold voltage, Body effect. MOS Device Design Equations, Basic DC equations,  Short Channel Effects and Device Models – Scaling Theory,  Threshold Voltage Variation, Mobility Degradation with Vertical Field, Velocity Saturation, Hot Carrier Effects, Output Impedance Variation with Drain- Source Voltage,  MOS Device Models, Small Signal AC Characteristics and  Modeling of MOS Transistors using SPICE. 

Unit – II: MOS INVERTERS: STATIC CHARACTERISTICS                     

9 lecture hours

Introduction, Voltage Transfer Characteristic (VTC),  Noise Immunity and Noise margins, Resistive-Load Inverter, Inverters with n-Type MOSFET Load and CMOS Inverter, DC Characteristics of CMOS Inverter, Calculation of  VIL, VIH, VOL, VOH and Vth,  Design of CMOS Inverters, Supply Voltage Scaling in CMOS Inverters, Power and Area considerations.

Unit – III: MOS INVERTERS: Switching Characteristics and Interconnect Effects 

9 lecture hours

Switching Characteristics of CMOS Inverter-  Delay-Time Definitions, CMOS Propagation Delay,  Calculation of Delay times, Estimation of Interconnect parasitic- Interconnect Capacitance Estimation, Interconnect Resistance Estimation, Layout of an Inverter,  Calculation of Interconnect Delay-  RC Delay Models,  The Elmore Delay,  Buffer Chains, Low Swing Drivers, Power Dissipation-Switching, Short-Circuit and Leakage Components of Energy and Power,  Power-Delay Product, Power Distribution and Performance Optimization of Digital Circuits by Logical Effort Sizing; CMOS Ring Oscillator Circuit.

Unit – IV: CMOS Logic Structures and Subsystem Design                               

9 lecture hours

COMBINATIONAL MOS LOGIC CIRCUITS- CMOS Logic Circuits (NAND, NOR and Complex Logic Gates, Multiplexers etc.), CMOS Transmission Gates (Pass Gates), Pseudo nMOS logic, Dynamic CMOS logic, Clocked CMOS logic and CMOS Domino logic.

SEQUENTIAL MOS LOGIC CIRCUITS-Behavior of Bistable Elements, The SR Latch Circuit, Clocked Latch and Flip-Flop Circuits, CMOS D-Latch and Edge-Triggered Flip-Flop.

Subsystem design process- design of 4-bit shifter, arithmetic building blocks like adders, multipliers and ALU.

Unit – V: SEMICONDUCTOR MEMORIES AND LOW-POWER CMOS LOGIC CIRCUITS  

9 lecture hours

Semiconductor memories: non-volatile and volatile memory devices, flash memories, SRAM Cell Design, Differential Sense Amplifiers, DRAM Design, Single Ended Sense Amplifier

Overview of Power Consumption, Low-Power Design Through Voltage Scaling, Estimation and Optimization of Switching Activity, Reduction of Switched Capacitance and Adiabatic Logic Circuits

Mode of Evaluation: The theory performance of students are evaluated separately.

 

Components Internal SEE
Marks 50 50
Total Marks 100
Scaled Marks 100

 

Relationship between the Course Outcomes (COs) and Program Outcomes (POs)

Mapping between Cos and Pos
Sl. No. Course Outcomes (COs) Mapped Programme Outcomes
1 MOS device structure and functions 1
2 CMOS characteristics , delay etc. 3
3 CMOS Logic Design 4
4 Low power VLSI and Semiconductor Memories 9

  

    Engineering Knowledge Problem analysis Design/development of solutions Conduct investigations of complex problems Modern tool usage The engineer and society Environment and sustainability Ethics Individual or team work Communication Project management and finance Life-long Learning
    1 2 3 4 5 6 7 8 9 10 11 12
TEC323 VLSI Technology 3   2 2         2      

1=addressed to small extent

2= addressed significantly

3=major part of course 

Theory  The theory of this course is used to evaluate the program outcome PO(3)
ADMISSIONS 2021